1. Technical Field
The present invention relates to a method of manufacturing a semiconductor substrate and a semiconductor device, and more particularly to a technique of forming an silicon on insulator (SOI) layer on a semiconductor substrate.
2. Related Art
A transistor formed on an SOI substrate has great advantages such as reducing the power consumption and increasing the operation speeds of the semiconductor device, because the transistor has a smaller junction capacitance (capacitance between a source/drain region and a substrate) than that of a transistor formed on a bulk silicon substrate.
In general, an SOI substrate including an SOI layer formed over the entire surface of a bulk silicon substrate is prepared, and transistors are subsequently formed on the SOI layer while the unnecessary portion of the SOI layer is removed.
Examples of methods to form an SOI substrate include: forming an SOI substrate by using a bonding technique as disclosed in JP-A-2002-299591, a first related art example; and forming an SOI substrate by using a separation by implanted oxygen (SIMOX) technique disclosed in JP-A-2000-124092, a second relate art example.
T. Sakai et al., Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004), is a third related art example.
The example discloses a SBSI (Separation by Bonding Si Islands) method, which partially forms an SOI layer on a bulk silicon substrate, allowing low-cost manufacture of SOI transistors.
In this method of forming an SOI layer on a bulk silicon substrate, a silicon germanium (SiGe) layer and a silicon (Si) layer are grown epitaxially on the silicon substrate, and then holes for forming a support (support hole) are formed through the layers.
A silicon oxide layer or the like, which is to become a support, is formed over the holes.
Then, in order to form an element region, portions of the silicon oxide layer, the silicon layer and the silicon germanium layer located in the vicinity the element region are dry etched away.
Further, when the silicon germanium layer is selectively etched with fluoro-nitric acid, a cavity is formed under the silicon layer that is supported by the support.
By burying in the cavity an insulating layer made of silicon oxide or the like, a buried oxide (BOX) layer is formed between the silicon substrate and the silicon layer.
A silicon oxide layer is then deposited on the silicon substrate.
Subsequently, the surface of the substrate is planarized by a CMP (Chemical-Mechanical Polishing) method or the like to make uniform the thickness of the silicon oxide layer located on the SOI layer, and then the SOI layer is exposed by using buffered fluoric acid or the like.
Thus the SOI layer is provided on the bulk silicon substrate.
Manufacturing a bonded substrate using the above-mentioned technique disclosed in the first related art example requires bonding two silicon substrates to each other and then polishing the surface of the silicon wafer.
It is therefore difficult to precisely control the thickness of a thin semiconductor layer the SOI structure has.
There is also a problem such that the price of the SOI substrate becomes higher than that of the bulk silicon substrate due to the bonding and polishing processes.
Manufacturing an SIMOX substrate using the above-mentioned technique disclosed in the second related art example requires ion implantation of oxygen of high concentration into a silicon wafer.
As a result, damage caused by the ion implantation can remain in the SOI substrate.
There is also a problem such that the ion implantation of oxygen of high concentration reduces the throughput of the SOI substrate and makes the price higher than that of the bulk silicon substrate.
In the method disclosed in the third related art example, a BOX layer is formed as described above and then a silicon oxide layer is deposited on a silicon substrate.
Subsequently, the substrate surface is planarized by etching the silicon oxide layer using a CMP method or the like, and then is etched with buffered fluoric acid or the like, exposing an SOI layer.
If a CMP method or the like of planarizing a substrate surface is used at this point, it is difficult to control the etching amount in the planarization process of the CMP method or the like without an etch stop layer that serves the control of the etching amount.
If the etching amount is excessive, etching of the CMP method or the like reaches the SOI layer, causing damage to the SOI layer.
If the etching amount is insufficient, the remaining silicon oxide layer on the SOI layer is thick.
This may cause the silicon oxide layer to remain in the process of exposing the SOI layer by etching the silicon oxide layer with a buffered fluoric acid or the like.
There is therefore a problem of deviation in gate film thickness of transistors and defects resulting therefrom, for example.